MARCELO SIERO
IdeasSiero Lab: CEO and Founder
UCSC: PhD Graduate Student
email: siero@ideassiero.com
http://www.ideassiero.com
(831) 335-5600

Marcelo Siero, is the CEO of IdeasSiero Lab. IdeasSiero Lab provides consulting expertise to Silicon Valley firms. He is currently working on a a Ph.D. on faster, lower power, Deep Learning Computer Architectures.

Marcelo brings 30 years+ of broad base experience in computer engineering. Among his accomplishments are creating the verification infrastructure for a family of 64-bit SPARC processors at HAL Computers a former startup backed by Fujitsu corporation. He pioneered and ran an Internet Service Provider Business for in the early 90's. He designed an early VLSI micro-architecture at Xerox PARC, to replace the CPU for the legendary Alto bit-mapped display processor. He was also in the team that successfully designed and launched to market the very first CMOS-based VLSI computer made by Hewlett Packard Corporation.

AREAS OF EXPERTISE


Software Development and Infrastructure Management
  • Tensorflow/Keras-based Deep Learning Software Kits for GPU clusters.
  • Scientific Programming Using CUDA (GPUs), Python, C++, Matlab, Tensorflow, and Perl.
  • GPU Enabled Computer Cluster Programming.
  • DSP for Image and Speech Technology.
  • Use of Imaging Software Libraries.
  • Compiler and System Software Development.
  • Understanding of Code generation/optimization techniques,
  • Linux-based System Administration
  • Linux Security Management.
Computer and VLSI Design, and CAD Tool Development
  • Design verification: functional, logic, circuit, and layout
  • CISC and RISC computer architecture definition, hardware, software and simulation.
  • Implementation of computer load-balanced farms for computer simulation/testing.
  • Digital design VLSI circuit design, testing.
  • Assembly and micro- programming programming and tool creation.
  • Use of SPICE, Cadence Virtuoso, Calibre(DRC/LVS/Parasitics), logic simulators.
Technical Documentation and Instruction
  • Technical documentation: software, hardware, VLSI CAD, computer technology.
  • Languages and other software tools: Python, Perl, C++, Verilog, and more.
  • Technical Training, Unix, Perl, Compilers, and many other subjects.


BUSINESS AND CONSULTING EXPERIENCE


Present-1982: IdeasSiero Lab, President
Present-2000: Recent Technology & Business Development Activities Founded and Implemented and provided technical support for the following ventures:
  • Artists.com: A new model for online distribution of Art.
  • Business With Pleasure: A Digital Print Shop and more.
  • Sign City: Wide Format printing and digitazation of art and more.
  • Houses.com: An information based model for selling Real Estate.

2000-1992: Infoserv Connections, President

    Internet service provider providing e-mail and Usenet news to the Internet community.
    Development of Powerful Mail Client Integrating Usenet News and MIME capable E-mail.
2001, Community Oriented Activities
    Member of Board of Directors / Executive Committees:
    • Monterey Bay Institute of Electrical and Electronic Engineers Subsection ('90-present)
    • Actor's Theater (Local Community Theater): Treasurer/Secretary
    • Monterey Bay International Trade Association
1999-1990: Teacher
    2000-1999: San Jose State University Extension, Teacher/Course Development
    1999-1993: Instruction Set, Teacher/Author
    1987-1985: Northeastern University, Teacher
    1978-1977: Ohlone Junior College, Teacher
    1973-1975: Hewlett Packard Corporation (teaching hardware and software)

  • Developed and taught courses on at the various institutions listed above on the following topics: Web programming, Perl, CGI, RISC Architecture, Compiler Design, Advanced Logic Design, Intel 8X86 Assembler, Unix System Administration, Unix for beginners, logic and micro-Processor design
  • Authored book anonimously: Programming with Perl and CGI


EMPLOYMENT HISTORY


Present-1980: IdeasSiero Lab: Chief Consultant.
1985-1980: National Semiconductor, System Software Advisor
  • researched design and development of RISC architecture
  • developed front-end for advanced optimizing Pascal compiler
  • developed disassembler, linker, and loader for 32000 family
  • analyzed the performance of 32000 family
  • developed and wrote Marketing Specifications For System 32000 Development System
  • performed competitive analysis and provided technical marketing expertise
  • wrote/presented papers; chaired conference sessions at Wescon, Compcon and others

1980-1978: XEROX Palo Alto Research Center, Member of Research Staff
  • defined VLSI processor architecture optimized for MESA language, including BitBlt graphics
  • simulated architecture for 32-bit processor design
  • designed VLSI NMOS 32K RAM chip (3 Xstor cell)
  • developed, implemented, and tested NMOS content addressable memory
  • supported SPICE-II circuit simulator (FORTRAN IV)
  • investigated development/acquisition of VLSI testers
  • developed custom-made purchase order, document tracking system
  • developed program for layout of regular LSI structures
1978-1973: Hewlett Packard Corporation, Member of Technical Staff
  • developed to completion and product release of CPU product (HP300/3000) using CMOS/SOI technology
  • designed (logic/layout/STA timing and Ckt design/testing) control section of RALU chip.
  • designed and documented Bus Interface Controller (BIC)
  • developed system micro-diagnostics for RASS chip and BIC
  • developed stuck-at-fault tests for fault checking and isolation of BIC
  • programmed automatic PLA logic simulator system
  • developed PROM burner system
  • taught programming and maintenance on 21Mx computer family


EDUCATION AND CREDENTIALS
  • PhD Student, UCSC (Research in Progress).
  • MS in Computer Engineering, UCSC.
  • BSEE from Cal State University, Long Beach
  • Junior College Teaching Credential in Math and Engineering
  • Many classes and seminars, Leadership (UCSC), Speech Recognition (ISIP at Mississippi State), Voice Synthesis (Festival at CMU and SPCC17), Logic Design and Synthesis/SOC (UCSC), Parallel Computing, Gaming Narrative (UCSC), Compiler Code Generation and Optimization (Stanford), Neuromorphic Computing (IBM), SCSD (Supercomputing Workshop at UCSD).


MISCELLANEOUS (EDUCATIONAL) PROJECTS
  • Design of 16-bit Multiplier using 190nm technology (UCSC project).
  • Logic Design for an SOC Satisfiability Processor, employing an integrated parallel latch/computation array, control and a Wishbone xface (UCSC project).
  • Implementation of 2D CUDA-accelerated convolver Unit for Optical Proximity Correction.
  • Neural network program for pattern recognition (Associatron)
  • Automatic Parser Generator - Table driven parser generator for a compiler front-end
  • Parser for Euler Language
  • Architect, design and construction of bit-slice RISC mini-computer
  • Editor, 49er Engineer Magazine (CSULB)


PERSONAL


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