Ideassiero Lab, formerly Innervision Computers

UCSC - University of California in Santa Cruz
Projects for Ph.D. coursework.

Tensorflow Cluster-based Deep Learning Benchmarking Systems:
Apply cluster-based acceleration techniques while applying novel performance analysis methodology, and explore new hardware acceleration ideas.

Open Source Kit for Voice Synthesis:
Festival, HTS and Merlin-based Speech Synthesis.

Typist Recognition System:
Wrote a Machine Learning program to recognize a typist from his typing patterns (delays between typed characters). The program achieved 75% accurate classification on a test involving 8 typists on a 10 paragraph sample. Primary technique used was AdaBoost, written in Matlab.

Convolution-based OPC Simulation:
Wrote a CUDA-based GPU convovler for simulating Optical Proximity Correction (OPC) of IC Masks that accelerated such simulation by a factor of 100 over that of a fast X86 processor with a single NVIDIA GTX580 GPU.

PTB Random Image Visual Stimulus Generator:
PsychoPhysics Tool Box-baed System involving Matlab, Cuda-accelerated Random Number Generator for providing Image Stimuli for characterization of mammalian retinas.

Montalvo Systems
Montalvo Systems is a well funded fabless semiconductor startup funded by prominent Silicon Valley V.C. firms.

Spice Navigator:
Developed a system for navigating large SPICE files and providing a computer assisted system for creating timing measurements in hierarchical and RC extracted models. This program also served as a powerful library to manipulate netlist within other tools.

Developed a donut maker program to provide accurate timing SPICE simulation accurately while dramatically reducing the total transistor count for large arrays of cells (specialized RAMs).

Provided tools to facilitate with the generation of patterns for SPICE simulation across multi-ported macros.

HAL Computers
HAL was one of the largest start-ups in Silicon Valley which later became a wholly owned subsidiary of Fujitsu. Its charter was to make very high-end high performance 64-bit SPARC processors. This contract spanned a period of eight years, ending in the year 2000. Innervision's contract was by far the longest standing contract awarded to a private consulting firm in the history of HAL. The work performed provided tools that became the the workhorse for verification and bring-up (JTAG based) for their state-of-the-art microprocessors for many years. The tools also evolved in being used for bring-up of these processors as well.

LDB – Logic Debugger System:
Conceived and developed a new paradigm for design verification of advanced computer architectures. The system implemented became widely used as the foundation for the verification platform used to test all models of VLSI processors developed at HAL. This system connected a variety of simulation platforms that HAL used to verify their microprocessors, including: a functional simulator and numerous different types of logic simulators such as Verilog VCS, and Hal’s own Aida simulator. Additional facilities were added for implementation of a logic to functional design comparator.

LDBRUN – Redundant Integrated Load-balancing Verification Platform:
Designed and developed a platform for the integration and load balancing of thousands of verification jobs on a farm of 500 networked computers. The system launched test jobs and collected and integrated test results. The system also detected failed jobs and provided redundant relaunching of jobs as needed to guarantee unsupervised results for overnight runs.

LDB/TISIM: Logic Debugger for Physical Hardware Bring up:
LDB was also extended to interface with a JTAG interface allowing the probing and setting the entire internal state of the processor. This tool became the primary vehicle used in the bring-up lab, to get bring the processors to life.

Both LDB and LDB/TISIM were built by creating a customized version of the PERL language, which made its use suitable for hardware simulation applications.

In addition there was a large variety of projects in the area of timing verification, logic verification and IC layout. and and Other Projects
Led a small team to design, implement and support the infrastructure for these sites, all the way from artistic design, to web site implementation, hosting and IT infrastructure and security. coding was implemented in: HTML, CSS, Javascript, Perl CGI, PHP, and MySQL. was implemented with ES16, Node.js, React and Redux. Graphics developed with Photoshop Creative Suite. Numerous other Wordpress-based projects including a Chamber of Commerce Web site, and an Art and Wine Artists event recruitment web site.

Porting of SPEC Benchmarks from Unix to Windows/NT (using Perl and a custom-made Make program).

Development of BAPCO benchmark management system, both a DOS and a Windows 3.1 version. Neither are Intel released products, and are getting extensive use in the industry. They were developed using Borland's Object Windows Library and C++.

Writing of Instruction set description chapter for 80386 Microprocessor Reference Manual including development of new notation and algorithmic description for instruction. The Instruction set description has been used in subsequent X86 instruction set manuals even onto present day.

Writing of chapter 1,2 and 3 of i860 Microprocessor Hardware Manual.

Infoserv Connections
Development of Windows-based email and newsreader program for operation on both LAN's and WAN's. This feature packed software suite possessed many features similar to Eudora and Microsoft Outlook. This was the first of such programs to include a very powerful newsreader system, early use of right mouse button, and implementation of MIME attachments. This served as the foundation for Infoserv's highly reliable e-mail service spanning a period of seven years.

Benchmarking of systems and embedded processors involving: Gmicro/200/300, AMD 29XXX, Motorola 680X0, SPARC, MIPS, as well as Vector Processing/RS6000 numerical performance studies based on Livermore Benchmarks. Analyze compiler code optimizations and architectural issues. C and C++ compiler functional testing and optimizer evaluation. Projects involved use of Gnu, MRI and Greenhill's compilers.

Cost/performance surveys of microprocessors and BitBlt graphics performance study.

Development and Installation of Member Tracking System based on Paradox for Windows/Object PAL on LANTASTIC network.

InnerVision Computers
Assembler and linker development for NS32000 dual processor system. Neural-net pattern recognition system.

VLSI CAD consulting.

User's manuals for DRACULA, SYMBAD, Parasitic Extractors, LVS and other VLSI CAD tools.

Hardware and software system design for milling machine-based Numerical Control.

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